
/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/
#include "r5_clk.h"


void Mcu_Bst_InitClock(void)
{

    unsigned long clk_sel = 0;

    //safety

    //st-clk_sel1
    clk_sel = REG32_READ(0xc0030000 + 0x04);

    clk_sel = (clk_sel & (~(SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_PCLK_MASK       |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_HCLK_MASK           |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_ACLK_MASK           |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CORESIGHT_CRM_CLK_MASK          |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_CSR_CLK_MASK             |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_MASK)))                  |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_PCLK(mux_clk_safenoc_pclk_clk_200m)         |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_HCLK(mux_clk_safenoc_hclk_clk_300m)         |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_ACLK(mux_clk_safenoc_gaclk_clk_600m)        |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CORESIGHT_CRM_CLK(st_main_clk_25m)                      |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_CSR_CLK(mux_clk_r5_csr_clk_200m)                 |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5(mux_clk_r5_1200m);

    REG32_WRITE(0xc0030000 + 0x4 , clk_sel);

    //st-clk_sel2
    clk_sel = REG32_READ(0xc0030000 + 0x08);

    clk_sel = (clk_sel & (~(SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SGMAC_PTP_CLK_MASK      |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_GAMC_MCLK_MASK              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SSP_PCLK_MASK               |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_PCLK_MASK              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_WCLK_MASK              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_QSPI_200M_MASK              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SRAM_600M_MASK              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_200M_MASK              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_400M_MASK              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_ADC_WCLK_MASK)))       |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SGMAC_PTP_CLK(mux_clk_div_clk_gmac_ptp_clk)         |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_GAMC_MCLK(mux_clk_gmac_mclk_lb_gamc_epp_rxclk_125m) |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SSP_PCLK(mux_clk_ssp_pclk_clk_200m)                 |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_PCLK(mux_clk_lsp0_pclk_clk_200m)               |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_WCLK(mux_clk_lsp0_wclk_clk_400m)               |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_QSPI_200M(mux_clk_qspi_clk_400m)                    |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SRAM_600M(mux_clk_sram_clk_600m)                    |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_200M(mux_clk_sdma_ghclk_clk_200m)              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_400M(mux_clk_sdma_gwclk_clk_400m)              |\
                        SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_ADC_WCLK(mux_clk_lsp0_adc_wclk_clk_500m);

    REG32_WRITE(0xc0030000 +0x8 , clk_sel);

    //realtime

    //rt-clk_sel0  
    REG32_WRITE(0xd1033000 + 0x90 , 0x7ff);

    //rt-clk_sel1
    clk_sel = REG32_READ(0xd1033000 + 0x94);

    clk_sel = (clk_sel & (~(RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIP_NIC_CLK_MASK       |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIP_NIC_CLK_MASK           |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIP_NIC_CLK_MASK           |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIS_NIC_CLK_MASK           |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIS_NIC_CLK_MASK           |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIS_NIC_CLK_MASK           |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_RTNOC_ACLK_MASK                  |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_1200M_MASK                  |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_1200M_MASK                  |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_1200M_MASK )))              |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIP_NIC_CLK(mux_clk_r5_2_axip_nic_clk_600m)    |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIP_NIC_CLK(mux_clk_r5_1_axip_nic_clk_600m)    |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIP_NIC_CLK(mux_clk_r5_0_axip_nic_clk_600m)    |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIS_NIC_CLK(mux_clk_r5_2_axis_nic_clk_600m)    |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIS_NIC_CLK(mux_clk_r5_1_axis_nic_clk_600m)    |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIS_NIC_CLK(mux_clk_r5_0_axis_nic_clk_600m)    |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_RTNOC_ACLK(mux_clk_rtnoc_aclk_600m)                  |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_1200M(mux_clk_r5_2_1200m_1200m)                 |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_1200M(mux_clk_r5_1_1200m_1200m)                 |\
                        RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_1200M(mux_clk_r5_0_1200m_1200m) ;

    REG32_WRITE(0xd1033000 + 0x94 , clk_sel);

    //rt-clk_sel2
    clk_sel = REG32_READ(0xd1033000 + 0x98);

    clk_sel = (clk_sel & (~(RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_APB0_PCLK_100M_MASK          |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA_NIC2X1_HCLK_MASK            |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_PCLK_MASK                   |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_WCLK_MASK                   |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_PCLK_MASK                   |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_WCLK_MASK                   |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_PCLK_200M_MASK             |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM1_600M_MASK                  |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM0_600M_MASK                  |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_RTDMA_400M_MASK                  |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_NIC2X1_HCLK_MASK )))             |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_APB0_PCLK_100M(mux_clk_apb0_pclk_100m_100m)          |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA_NIC2X1_HCLK(mux_clk_sdma_nic2x1_hclk_400m)      |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_PCLK(mux_clk_lsp1_pclk_200m)                    |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_WCLK(mux_clk_lsp1_wclk_400m)                    |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_PCLK(mux_clk_lsp0_pclk_200m)                    |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_WCLK(mux_clk_lsp0_wclk_400m)                    |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_PCLK_200M(mux_clk_sdma0_pclk_200m_400m)        |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM1_600M(mux_clk_sram1_600m_600m)                  |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM0_600M(mux_clk_sram0_600m_600m)                  |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_RTDMA_400M(mux_clk_rtdma_400m_400m)                  |\
                        RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_NIC2X1_HCLK(mux_clk_nic2x1_hclk_600m);

    REG32_WRITE(0xd1033000 + 0x98 , clk_sel);

    //switch

    clk_sel = REG32_READ(0x217b0000 + 0x90);

    clk_sel = (clk_sel & (~(SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_APB_CLK_MASK              |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_AXI_CLK_MASK                  |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_APB_CLK_MASK                 |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_AXI_CLK_MASK                 |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI2_CLK_MASK                  |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI1_CLK_MASK                  |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI0_CLK_MASK                  |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB4_5_CLK_MASK                |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB2_3_CLK_MASK                |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB0_1_CLK_MASK                |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC4_5_CLK_MASK                |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC2_3_CLK_MASK                |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC0_1_CLK_MASK                |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE4_5_CLK_MASK               |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE2_3_CLK_MASK               |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE0_1_CLK_MASK)))            |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_APB_CLK(mux_clk_sw_epp_apb_clk_200m)          |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_AXI_CLK(mux_clk_sw_epp_axi_clk_600m)          |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_APB_CLK(mux_clk_sw_gmac_apb_clk_200m)        |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_AXI_CLK(mux_clk_sw_gmac_axi_clk_200m)        |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI2_CLK(mux_clk_sw_r5_ppi2_clk_600m)          |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI1_CLK(mux_clk_sw_r5_ppi1_clk_600m)          |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI0_CLK(mux_clk_sw_r5_ppi0_clk_600m)          |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB4_5_CLK(mux_clk_sw_r5_apb4_5_clk_200m)      |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB2_3_CLK(mux_clk_sw_r5_apb2_3_clk_200m)      |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB0_1_CLK(mux_clk_sw_r5_apb0_1_clk_200m)      |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC4_5_CLK(mux_clk_sw_r5_nic4_5_clk_600m)      |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC2_3_CLK(mux_clk_sw_r5_nic2_3_clk_600m)      |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC0_1_CLK(mux_clk_sw_r5_nic0_1_clk_600m)      |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE4_5_CLK(mux_clk_sw_r5_core4_5_clk_1200m)   |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE2_3_CLK(mux_clk_sw_r5_core2_3_clk_1200m)   |\
                        SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE0_1_CLK(mux_clk_sw_r5_core0_1_clk_1200m);

    REG32_WRITE(0x217b0000 + 0x90 , clk_sel);

    clk_sel = REG32_READ(0x217b0000 + 0x94);

    clk_sel = (clk_sel & (~(SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_AXI_CLK_MASK                      |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CORE_CLK_MASK                         |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CFG_CLK_MASK                          |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SYSCTRL_CSR_CLK_MASK                       |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_FLEXRAY_AHB_NIC_BRIDGE_CLK_MASK            |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_STANDBY_SRAM_CLK_MASK                      |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM1_CLK_MASK                             |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM0_CLK_MASK                             |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_DMA_CLK_MASK                               |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_CLK_MASK             |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_AXI_CLK_MASK         |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_FLEXRAY_AHB_CLK_MASK                   |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_WORK_CLK_MASK                      |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_WORK_CLK_MASK                          |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_APB_CLK_MASK                       |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_PCS_APB_CLK_MASK)))                    |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_AXI_CLK(mux_clk_sw_sdma_axi_clk_400m)                                        |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CORE_CLK(mux_clk_sw_sdma_core_clk_400m)                                      |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CFG_CLK(mux_clk_sw_sdma_cfg_clk_200m)                                        |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SYSCTRL_CSR_CLK(mux_clk_sw_sysctrl_csr_clk_200m)                                  |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_FLEXRAY_AHB_NIC_BRIDGE_CLK(mux_clk_sw_flexray_ahb_nic_bridge_clk_400m)            |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_STANDBY_SRAM_CLK(mux_clk_sw_standby_sram_clk_200m)                                |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM1_CLK(mux_clk_sw_sram1_clk_600m)                                              |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM0_CLK(mux_clk_sw_sram0_clk_600m)                                              |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_DMA_CLK(mux_clk_sw_dma_clk_400m)                                                  |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_CLK(mux_clk_sw_security_acceleration_clk_600m)              |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_AXI_CLK(mux_clk_sw_security_acceleration_axi_clk_600m)      |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_FLEXRAY_AHB_CLK(mux_clk_sw_lsp_flexray_ahb_clk_200m)                          |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_WORK_CLK(mux_clk_sw_lsp_can_work_clk_400m)                                |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_WORK_CLK(mux_clk_sw_lsp_work_clk_200m)                                        |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_APB_CLK(mux_clk_sw_lsp_can_apb_clk_600m)                                  |\
                        SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_PCS_APB_CLK(mux_clk_sw_lsp_pcs_apb_clk_200m);

    REG32_WRITE(0x217b0000 + 0x94 , clk_sel);

    clk_sel = REG32_READ(0x217b0000 + 0x98);

    clk_sel = (clk_sel & (~(SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_MASK                   |\
                        SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_DIV_CLK_MASK           |\
                        SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_MUX_CLK_MASK           |\
                        SW_CRM_CSR_SW_CLK_SEL2_APBSW_CLK_SEL_MASK                                |\
                        SW_CRM_CSR_SW_CLK_SEL2_NOC_CLK_SEL_MASK                                  |\
                        SW_CRM_CSR_SW_CLK_SEL2_CRM_CLK_SEL_MASK)))                               |\
                        SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL(mux_clk_sw_ptp_clk_sel_ptp_div_clk)                                      |\
                        SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_DIV_CLK(mux_clk_sw_ptp_clk_sel_ptp_div_clk_ptp_mux_clk)              |\
                        SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_MUX_CLK(mux_clk_sw_ptp_clk_sel_ptp_mux_clk_input_clk_pad_ptp_clk)    |\
                        SW_CRM_CSR_SW_CLK_SEL2_APBSW_CLK_SEL(apbsw_clk_sel_200m)    |\
                        SW_CRM_CSR_SW_CLK_SEL2_NOC_CLK_SEL(noc_clk_sel_600m)        |\
                        SW_CRM_CSR_SW_CLK_SEL2_CRM_CLK_SEL(crm_clk_sel_200m) ;

    REG32_WRITE(0x217b0000 + 0x98 , clk_sel);

}
